Exemplary embodiments of the present invention relate to an integrated circuit, and more particularly, to a delay locked loop of a semiconductor memory device and a driving method thereof.
Semiconductor memory devices, such as a dynamic random access memory (DRAM), have continuously improved in their integration density and operating speed. In order to increase the operating speed, synchronous memory devices designed to operate in synchronization with clocks provided from the outside of memory chips (i.e., external clocks) have been developed. Such synchronous memory devices may use a delay locked loop (DLL) to generate an internal clock by delaying an external clock for a predetermined time so that data are outputted exactly in synchronization with rising and falling edges of the external clock.
A DLL generates an internal clock in which a delay element inside a memory device is compensated for synchronization with an external clock. This process performed by the DLL is called delay locking. A delay locked state refers to a state in which a reference clock (REFCLK) and a feedback clock (FBCLK) are synchronized with each other. A typical DLL achieves the synchronization between a feedback clock (FBCLK) and a reference clock (REFCLK) by adjusting a delay amount.
FIG. 1 is a block diagram of a typical DLL.
Referring to FIG. 1, the DLL includes a buffering unit 100, a phase comparison unit 110, a delay control unit 120, a variable delay unit 130, and a delay model unit 140.
The buffering unit 100 is configured to buffer an external clock EXTCLK and transfer the buffered external clock to the DLL as a reference clock REFCLK. The phase comparison unit 110 is configured to compare a phase of the reference clock REFCLK with a phase of a feedback clock FBCLK, and the delay control unit 120 is configured to generate a delay control signal CTR in response to an output signal of the phase comparison unit 110. The variable delay unit 130 is configured to delay the reference clock REFCLK in response to the delay control signal CTR. The delay model unit 140 is configured to reflect a delay of an actual clock/data path of an output signal of the variable delay unit 130 and output the feedback signal FBCLK.
The feedback clock FBCLK is a clock in which the reference clock REFCLK is adjusted by a delay time of the variable control unit 130 and a delay time of the delay model unit 140. The DLL compares the reference clock REFCLK with the feedback clock FBCLK and outputs a desired DLL clock DLLCLK when the two clocks have minimum jitters That is, the DLL outputs a DLL clock DLLCLK when delay locking is achieved.
Such a DLL having a conventional closed loop structure must undergo a feedback operation several times until delay locking is achieved. Consequently, a lot of time may be taken to achieve delay locking, and thus, a large amount of current may be consumed.